.SUBCKT SSCS3002S 4 5 6
*   created by Jacek Korek © Silicon Semiconductor March 4, 2004

M1  3 1 2 2 NMOS W=525.4E4u L=0.25u 
RDD 3 4     RTEMP 1.08E-3
CGS 1 2     1230E-12
DBD 2 3     DBD
RBD 2 3     1E9

CGD 1 8	8E-12
DGD 1 8	DGD
CDG 3 8	1150E-12
DDG 3 8	DDG

RGG 5 1     0.8E0
RSS 6 7     1.3E-3
LSS 7 2     1.5E-9

******************************************************************* 
.MODEL  NMOS       NMOS ( LEVEL  = 3               TOX    = 5E-8
+ RS     = 0.46E-3         RD     = 0               NSUB   = 1.25E17 
+ KP     = 3.3E-6         UO     = 500             
+ VMAX   = 0              XJ     = 0.3E-6          KAPPA  = 1E-5
+ ETA    = 1E-4           TPG    = 1  
+ IS     = 0              LD     = 0               
+ CGSO   = 0              CGDO   = 0               CGBO   = 0 
+ NFS    = 1E11           DELTA  = 0.1)
******************************************************************* 
.MODEL DBD D (CJO=2690E-12 VJ=0.7 M=0.52
+RS=0.1 FC=0.5 IS=1E-12 TT=5E-8 N=1 BV=37)
*******************************************************************
.MODEL DGD D (CJO=1150E-12 VJ=0.4 M=1.54
+ FC=0.5 IS=1E-12 )
*******************************************************************
.MODEL DDG D (CJO=10E-12 VJ=0.4 M=1.54
+ FC=0.5 IS=1E-12 )
******************************************************************* 
.MODEL RTEMP RES (TC1=6.E-3  TC2=6.E-6)
******************************************************************* 
.ENDS